The present invention relates to semiconductor devices, and more specifically, to the deposition of materials on high-mobility semiconductor layers.
Highly scaled device architecture such as FinFETs and Nanowires require a conformal high-quality gate stack to enable uniform electrostatic control. This is particularly challenging for the key interface layer of high mobility semiconductors such as InGaAs or (Si)Ge which possess low quality native oxides and have limited temperature process windows of up to 400 and 800 degrees Celsius, respectively, when their surfaces is exposed. In addition, monolithic CMOS integration with dual channels, e.g. InGaAs nFET & (Si)Ge pFET, generate complexity and limiting the number of process steps including lithography, masking, and etching by using deposition selectivity will reduce cost and increase yield.